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| Large Current External FET Controller Type Switching Regulators Step-down,High-efficiency Switching Regulators (Controller type) BD9018KV No.10028EAT15 Overview The BD9018KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It supports a wide input range and leads to eco-design (low power consumption) for various electronics. Features 1) Wide input voltage range: 3.9V30V 2) Precision voltage references: 0.8V1% 3) FET direct drive 4) Rectification switching for increased efficiency 5) Variable frequency: 250k550kHz (external synchronization to 600kHz) 6) Built-in auto-recovery over-current protection 7) Separate enable-pins per CH for individual power up/down control 8) Supports various applications: step-down, step-up, and step-up-down 9) Small footprint packages: VQFP48C 10) When operating at Max Duty, the switching frequency slows down to 1/5 to reduce input/output difference. Applications Car audio and navigation systems, CRTTVLCDTVPDPTVSTBDVDand PC systemsportable CD and DVD players, etc. Absolute Maximum Ratings (Ta=25) Parameter VCC Voltage EXTVCC Voltage VCCCL1,2 Voltage CL1,2 Voltage SW1,2 Voltage BOOT1,2 Voltage BOOT1,2-SW1,2 Voltage EN1,2 Voltage VREG5,5A Symbol VCC EXTVCC VCCCL1,2 CL1,2 SW1,2 BOOT1,2 Rating 35 35 35 *1 *1 *1 Unit V V V V V V Parameter PGOOD Voltage SS1,2 Voltage FB1,2 Voltage COMP1,2 Voltage RT Voltage SYNC Voltage Power Dissipation Symbol PGOOD SS1,2 FB1,2 COMP1,2 RT SYNC Pd Topr Tstg Tj Rating 7 Unit V 35 35 40 *1 *1 VREG5 V 1.1 *2 W BOOT1,2-SW1,2 7 *1 V Operating temperature Storage temperature Junction temperature -40+85 -55+150 +150 EN1,2 VREG5,5A EXTVCC 7 V V *1 Regardless of the listed rating, do not exceed Pd in any circumstances. *2 Mounted on a 70mm x 70mm x 1.6mm glass-epoxy board. Reduce by 8.8mW/ (VQFP48C) above 25. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 1/16 2010.02 - Rev.A BD9018KV Recommend operating range (Ta=25) Parameter Input voltage 1 Input voltage 2 BOOTSW voltage Oscillator frequency Synchronous frequency Synchronous frequency pulse width (ON Time) Synchronous frequency pulse width (OFF Time) Symbol VCC,EXTVCC VCCCL BOOTSW OSC SYNC Ton Toff Min. 3.9 *1 *2 3 *1 *2 Technical Note Typ. 12 12 5 300 1/(2xSYNC) 1/(2xSYNC) Max. 30 VCC VREG5 550 600 *2 - Unit V V V kHz kHz sec sec 3.9 250 OSC 0.2 0.2 *1 In case of using less than 6V, Short VCC, EXTVCC and VREG5. Moreover, it is the voltage range when 4.5V or greater is once supplied to the input. *2 Should not exceed OSCx2 This product is not designed to provide resistance against radiation. Electrical characteristics (Unless otherwise specified, Ta=25 VCC=12V STB=5V EN1,2=5V) Parameter VIN bias current Shutdown mode current EN1,2 low voltage EN1,2 high voltage Symbol IIN IST VENth1 VENth2 Min. GND 2.6 12 4.7 3.5 100 270 GNC 2.5 10 0.792 6.5 0.6 2.05 70 0.46 0.51 0.56 0.874 Limit Typ. 5 0 23 4.95 3.7 200 300 500 20 0.800 10 1.7 2.25 90 0.56 0.61 0.7 0 0.92 Max. 10 10 1.0 Vcc 48 5.2 3.9 400 330 0.5 7 40 1 0.808 13.5 3 2.45 0.3 110 10 0.66 0.71 3 0.966 Unit mA A V V A V V mV kHz kHz V V A A V A mA V V V A V V mA A V VSS=1V VSS=1V,VCC=3V VCC=0.3V Conditions EN1,2 input current IEN VREG5 Block VREG5 output voltage VREG5 Under Voltage Lock Out Block VREG5 threshold voltage VREG_UVLO VREG5 hysteresis voltage DVREG_UVLO Oscillator Oscillator frequency FOSC Synchronous frequency Fsync SYNC pulse low voltage Vsynclow SYNC pulse high voltage Vsynchigh SYNC input current Isync Error Amp Block VO input bias current IVo+ Feedback reference voltage VOB Soft start block Charge current ISS Discharge current IDIS Maximum voltage Vss_MAX Standby voltage Vss_STB Over Current Protection Block CL threshold voltage Vswth CL input current 1,2 Iswin Output short detection voltage Vosh Output short release voltage Vodet PGOOD PGOOD output L current IPGOODL PGOOD output H current IPGOODH Over voltage detection voltage VFBO EN1,EN2=0V , VREG5 OFF When each EN is OFF, each ch is OFF When EN is ON, each ch is ON VEN=5V IREF=6mA VREG:Sweep down VREG:Sweep up RT=100 k RT=100 k,SYNC=500kHz Vsync=5V VFB VFB PGOOD=1V,FB=0V PGOOD=5V VFB www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 2/16 2010.02 - Rev.A BD9018KV Reference data (Unless otherwise specified, Ta=25) 100 90 Standby current Istb [uA] 10 9 10 9 Circuit c urrent Icc [mA] 8 7 6 5 4 3 2 1 0 0 10 20 30 0 10 Technical Note 80 EFFICIENCY [%] 70 60 50 40 30 20 10 0 0 5 .0 V 3 .3 V 8 7 6 5 4 3 2 1 0 VIN=12V 1 2 OUTPUT CURRENTIo [A] 3 20 30 Input voltage Vin [V] Input voltage Vin [V] Fig.1 Efficiency 1 Fig.2 Standby current Fig.3 Circuit current 808 REFERENCE VOLTAGE VOB [V] 806 804 802 800 798 796 794 792 -40 -15 10 35 60 85 AMBIENT TEMPERATURE Ta [] CL Threshold v oltage Vswth [mV] 11 0 OUTPUT VOLTAGE Vo [V] 11.0 10.5 10.0 9.5 9.0 8.5 8.0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE Ta[] 10 0 90 80 70 60 -40 -15 10 35 60 85 AMBIENT TEMPERATURE Ta [] Fig.4 Reference voltage vs. temperature characteristics 1 1.0 REFERENCE VOLTAGE VOB [ V] Fig.5 Over current detection vs. temperature characteristics 8 08 EN Threshold v oltage VEN [V] 8 06 8 04 8 02 8 00 7 98 7 96 7 94 7 92 -40 - 15 10 35 60 85 AMBIENT TEMPERATURE Ta [] Fig.6 Frequency vs. temperature characteristics 2.5 OUTPUT VOLTAGE Vo [ V] 1 0.5 1 0.0 9.5 9.0 8.5 8.0 - 40 2.0 1.5 1.0 0.5 -15 10 35 60 85 0.0 -40 - 15 10 35 60 85 AMBIENT TEMPERATURE Ta [ ] AMBIENT TEMPERATURE Ta [] Fig.7 SS Charge current vs temperature characteristics 7 6 Circuit c urrent Icc [mA] 5 4 3 2 1 0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE Ta [] Fig.8 UVLO threshold voltage vs temperature characteristics Fig.9 EN threshold voltage vs temperature characteristics Fig.10 Circuit current vs temperature characteristics www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 3/16 2010.02 - Rev.A BD9018KV Block diagram EXTVCC 41 Technical Note VCC 7 RT 33 SYNC 34 Reg VREG5 44 EN B.G SYNC UVLO TSD TSD OSC 8 VCCCL2 CL2 BOOT2 OUTH2 SW2 5 3 2 1 10 VCCCL1 CL1 BOOT1 OUTH1 SW1 VREG5A OUTL1 DGND1 FB1 SS1 OCP Set DRV Reset Reset Set DRV OCP 11 12 48 VREG5 SW LOGIC TSD UVLO PWM COMP TSD UVLO SW LOGIC 13 17 15 14 21 23 OUTL2 DGND2 FB2 SS2 46 PROTECT OCP Slope Slope PWM COMP PROTECT LOGIC OCP 47 39 37 LOGIC Err Amp Err Amp UVLO COMP2 38 Q Set Reset Q Set Reset 22 COMP1 det 36 27 26 PGOOD EN2 EN1 Fig. 11 Pin configuration PIN function table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name OUTH2 BOOT2 CL2 N.C VCCCL2 N.C VCC VCCCL1 N.C CL1 BOOT1 OUTH1 SW1 DGND1 OUTL1 N.C VREG5A N.C N.C N.C FB1 COMP1 SS1 N.C N.C EN1 EN2 N.C N.C GNDS N.C N.C RT SYNC N.C PGOOD SS2 COMP2 FB2 N.C EXTVCC N.C N.C VREG5 N.C OUTL2 DGND2 SW2 Function High side FET gate drive pin 2 OUTH2 driver power pin Over current detection pin 2 Non-connect (unused) pin Over current detection VCC2 Non-connect (unused) pin Input power pin Over current detection CC1 Non-connect (unused) pin Over current detection setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 Non-connect (unused) pin FET drive REG input Non-connect (unused) pin Non-connect (unused) pin Non-connect (unused) pin Error amp input 1 Error amp output 1 Soft start setting pin 1 Non-connect (unused) pin Non-connect (unused) pin Output 1 ON/OFF pin Output 2 ON/OFF pin Non-connect (unused) pin Non-connect (unused) pin Ground Non-connect (unused) pin Non-connect (unused) pin Switching frequency setting pin External synchronous pulse input pin Non-connect (unused) pin Power good terminal Soft start setting pin 2 Error amp output 2 Error amp input 2 Non-connect (unused) pin External power input pin Non-connect (unused) pin Non-connect (unused) pin FET drive REG output Non-connect (unused) pin Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 PGOOD SYNC GNS EN2 EN1 26 N.C N.C N.C N.C N.C 36 35 34 33 32 31 30 29 28 27 N.C 25 24 N.C 23 SS1 22 COMP1 21 FB1 20 N.C 19 N.C 18 N.C 17 VREG5A 16 N.C 15 OUTL1 14 DGND1 13 SW1 12 SS2 37 COMP2 38 FB2 39 N.C 40 EXTVCC 41 N.C 42 N.C 43 VREG5 44 N.C 45 OUTL2 46 DGND2 47 SW2 48 1 2 3 4 5 6 7 8 9 10 11 RT VCC VCCCL1 BOOT2 BOOT1 N.C N.C OUTH2 N.C VCCCL2 Fig. 12 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. OUTH1 CL2 CL1 4/16 2010.02 - Rev.A BD9018KV Block functional descriptions Technical Note Error amp The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage. Oscillator (OSC) Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250 kHz and 550 kHz. The phase difference between each output is 180deg. SLOPE The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator. PWM COMP The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum. Reference voltage (VREG5) This block generates the internal reference voltage: 5V. The external capacitor is necessary for VREG5. Moreover, the external capacitor should be set to VREG5A which is FET drive REG input. It is recommended to use the ceramic capacitor that is low ESR and 6.6F12 F according to VREG5 and VREG5A. External synchronization (SYNC) When pulses are supplied to the SYNC terminal, the internal frequency synchronizes with the frequency of the supplied pulses. When synchronized with SYNC, 1ch is turned on with the rising edge of SYNC and 2ch is turned on with the falling edge of SYNC so that the phase difference between each output depends on the Duty of SYNC. The pulse width needs to be more than 200nsec for both on time and off time. Supply a pulse wave faster than the frequency determined with the setting resistor (RT), but slower than 600 kHz (Foscx1.5 or less). Moreover, it is recommended to insert the low pass filter to the SYNC terminal. (Refer to Fig.13) Over current protection (OCP) The over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When the over current protection is active, Duty is low, and the output voltage also decreases. Short circuit protection (SCP) After activating the over current protection and if the output voltage falls below 70%, then the short circuit protection will be activated. When the short circuit protection is active, the output is turned off for 32 pulses of the oscillation frequency, and the SS and COMP are discharged. Protection circuits (UVLO/TSD) The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or exceeds 150. Output is restored when the temperature drops below the threshold value. Power GOOD (PGOOD)terminal The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or exceeds 150. Output is restored when the temperature drops below the threshold value. Application circuit example 100uF VIN(12V) 23m 100 1nF 23m 100 1nF SP8K2 RB160 VA-40 1uF SP8K2 RB160 VA-40 12 11 10 8 7 5 3 2 1 (SLF10145TDK) Vo(3.3V/2A) 10uH RB051 L-40 (SLF10145TDK) 0.1 uF 10uH RB051 L-40 BOOT1 VCCCL1 0.1 uF OUTH1 13 14 15 VCCCL2 BOOT2 CL1 VCC CL2 OUTH2 SW2 DGND2 OUTL2 VREG5 48 47 46 44 Vo(5V/2A) SW1 DGND1 OUTL1 3300pF 150 47k 30uF (C2012JB 0J106K TDK) 30uF 4.7uF (C2012JB 0J106K TDK) 68 k 1000pF 510 17 4.7uF 21 VREG5A 15k 10000pF 330pF 22 FB1 COMP1 SS1 SYNC GND EN1 EN2 RT EXTVCC FB2 COMP2 SS2 PGOOD 36 41 39 1uF 330pF 13k 3.3k 3300pF 22nuF 1k 22nF 23 38 37 26 27 30 33 34 33pF 100k 2k Fig. 13Step-Down There are many factors (PCB board layout, Output Current, etc.) that can affect the DCDC characteristics. Please verify and confirm using practical applications. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 5/16 2010.02 - Rev.A BD9018KV Application component selection (1) Setting the output L value Technical Note The coil value significantly influences the output ripple current. IL Thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lower the drop in ripple current. IL = VCC-VOUTxVOUT LxVCCxf [A] 5 Fig. 14 VCC IL L VOUT The optimal output ripple current setting is 30% of maximum current. IL = 0.3xIOUTmax.[A] 6 L= VCC-VOUTxVOUT ILxVCCxf [H] 7 Co Fig. 15 Output ripple current ILoutput ripple current fswitching frequency Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. It is recommend establishing sufficient margin to ensure that peak current does not exceed the coil current rating. Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency. (2) Setting the output capacitor Co value Select output capacitor with consideration to the ripple voltage (Vpp) tolerance. The following equation is used to determine the output ripple voltage. IL Step down VPP = IL x RESR + Co x Vcc Vo x f 1 [V] Note: fswitching frequency Be sure to keep the output Co setting within the allowable ripple voltage range. Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable lower output ripple voltage. Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. TSS x (Limit - IOUT) Co VOUT Tss soft start time 9 ILimitover current detection value Refer to 8/16 Note: less than optimal capacitance values may cause problems at startup. (3) Setting the Input capacitor Cin value VIN Cin VOUT L Co The input capacitor serves to lower the output impedance of the power source connected to the input pin (VCC). Increased power supply output impedance can cause input voltage (VCC) instability, and may negatively impact oscillation and ripple rejection characteristics. Therefore, be certain to establish an input capacitor in close proximity to the VCC and GND pins. Select a low-ESR capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. The ripple current IRMSS is determined using equation (10). 10 VOUTVCC - VOUT [A] VCC Also, be certain to ascertain the operating temperature, load range and MOSFET conditions for the application in which the capacitor will be used, since capacitor performance is heavily dependent on the application's input power characteristics, substrate wiring and MOSFET gate drain capacity. IRMS = IOUT x Fig. 16 Input capacitor www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 6/16 2010.02 - Rev.A BD9018KV Technical Note (4) Feedback resistor design Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range between 10k and 330k(total of R1 and R2). Resistance less than 10k risks decreased power efficiency, while setting the resistance value higher than 330k will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Also when the output pulse width is too short, there is a possibility the output becomes unstable. It is recommend putting the load more than half of the ripple current on the output or using the output pulse width longer than 250nsec. Vo Internal ref. 0.8V R1 FB Vo = Vo Vin Fig. 17 R1 + R2 R2 x 1 f x 0.8 [V] 11 R2 250nsec 12 For applications where Vin and EN are directly connected, the output may overshoot. To avoid this issue it is recommended to select the lower side of the feedback resistor to more than 47k. This restriction does not apply if the EN is individually turned on when the VCC is greater than 4.5V. (5) Setting switching frequency The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper RT resistance, noting that the recommended resistance setting is between 50k and 130k. Settings outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when unsupported resistance values are used. 600 550 500 frequency [kHz] 450 400 350 300 250 40 50 60 70 80 RT[k] 90 100 110 120 130 Fig. 18 RT vs. switching frequency www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 7/16 2010.02 - Rev.A BD9018KV Technical Note (6) Setting the soft start time The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (13) at right. 10 DELAY TIME[ms] 1 0.8V(typ.)xCSS TSS = ISS(10A Typ.) [sec](13) 0.1 0.01 0.001 0.01 SS CAPACITANCE[uF] 0.1 Fig. 19 SS capacitance vs. delay time Recommended capacitance values are between 0.01uF and 0.1uF. There is a possibility that the overshoot is generated in the output according to the phase compensation and the output capacity, etc. , and let me confirm it with a real machine, please. For the case with larger capacitance, the SS-pin may not become fully discharged when the EN becomes from H to L, which might cause the output overshoot when the EN becomes back H. Hence the discharge time (Tdis) needs to be carefully considered. Css x Vss_MAX Tdis = [sec] Idis The insertion of the CR filter is recommended as a noise measures because similar is thought when the noise enters the terminal EN. Please use high accuracy components (such as X5R) when implementing sequential startups involving other power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input voltage, output voltage and capacitance, coils and other characteristics. (7) Setting over current detection values The current limit valueILimitis determined by the resistance of the RCL established between CL and VCCCL. VCCCL CL VIN RCL IL L Vo IL Over current detection point 90m ILimit = RCL [A](14) Fig. 20 Fig. 21 The current limit is an auto-recovery type. When the over current is detected, the output Duty is reduced to limit the output current. The output voltage returns to normal when the load returns to the normal state. VoV 6 5 4 3 2 1 0 0 1 2 Fig. 22 3 4 5 IoA 6 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 8/16 2010.02 - Rev.A BD9018KV Technical Note (8) Method for determining phase compensation In switching regulator applications, the phase needs to be compensated in accordance with the operating conditions as well as the used external parts. In case the margin is not enough, then the output may possibly overshoot or undershoot when the load current, input voltage or switching frequency rapidly changes. The compensation technique is described below. Conditions for application stability Feedback stability conditions are as follows: At the unity (0-dB) gain, the phase delay is 150 or less (i.e., phase margin is at least 30): Since the DC/DC converter application is sampled according to the switching frequency, GBW (frequency at 0-dB gain) of the overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted characteristics of this application. At the unity (0-dB) gain, the phase delay is 150 or less (i.e. the phase margin is 30 or more). The GBW for this occasion is 1/10 or less of the switching frequency. Responsiveness is determined with restrictions on the GBW. To improve responsiveness, higher switching frequency should be provided. The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay (-180) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the application. GBW (the frequency at unity gain) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger capacitor will serve to lower GBW if desired. General use integrator (low-pass filter) Integrator open loop characteristics A (a) -20dB/decade GBW(b) -90 Phase margin Fig. 24 -180 1 2RCA Feedback R FB A COMP 0 0 Phase 0 [deg] -90 -9 0 -18 0 -180 Gain [dB] 18 0 point (a) fa = 1.25[Hz] 90 point (b) fa = GBW 1 [Hz] 2RC C Fig. 23 The error amp is provided with phase compensation similar to that depicted in figures and above and thus serves as the system's low-pass filter. In DC/DC converter applications, R is established parallel to the feedback resistance. When electrolytic or other high-ESR output capacitors are used: Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several ). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these locations is -180. However, wherever ESR is present, a 90 phase lead is generated, limiting the net phase margin to -90 in the presence of ESR. Since the desired phase margin is in a range less than 150, this is a highly advantageous approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components. LC resonance circuit Vcc ESR connected Vcc Vo L C Vo L C RESR Fig. 25 fr = 1 2LC [Hz] fr = Fig. 26 1 2LC 1 2RESRC [Hz]Resonance Point [Hz] :Phase lead Resonance point phase delay-180 fESR = Phase delay-90 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 9/16 2010.02 - Rev.A BD9018KV Technical Note Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose one of the following methods to add the phase lead. Add C to feedback resistor Vo C1 R1 FB R2 A COMP R2 C2 R1 FB A COMP Vo Add R3 to aggregator R3 C2 Fig. 27 Phase lead fz = 1 2C1R1 [Hz] Fig. 28 Phase lead fz = 1 2C2R3 [Hz] Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance. When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor: Where low-ESR (on the order of tens of m) output capacitors are employed, a two phase-lead insertion scheme is required, but this is different from the approach described in figure , since in this case the LC resonance gives rise to a 180 phase margin/delay. Here, a phase compensation method such as that shown in figure below can be implemented. Phase compensation provided by secondary (dual) phase lead Vo R1 C1 R3 FB A R2 COMP C2 Phase lead fz1 = Phase lead fz2 = 1 2R1C1 1 2R3C2 [Hz] [Hz] [Hz] LC resonance frequency fr = 1 2LC Fig. 29 Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency. This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount of trial-and-error process. There are many factors (The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 10/16 2010.02 - Rev.A BD9018KV 9MOSFET selection VCC VDS VGSM1 Technical Note IL Vo VGSM2 VDS Fig. 30 FET uses Nch MOS VDSVcc VGSM1Voltage between BOOT and SW pins VGSM2VREG5 Allowable currentvoltage current + ripple current Should be at least the over current protection value Select a low ON-resistance MOSFET for highest efficiency The shoot-through may happen when the input parasitic capacitance of FET is extremely big. Less than or equal to 1200pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this character is affected by PCB layout and components. 10Schottky barrier diode selection VCC Reverse voltage VRVcc Allowable currentvoltage current + ripple current Should be at least the over current protection value Select a low forward voltage, fast recovery diode for highest efficiency Vo VR Fig. 31 VO DC/DC converter controller + + RL Vm Maximum load Load 0 Output voltage Adequate phase margin 0 Inadequate phase margin t Fig. 32 Please contact us if you have any questions regarding phase compensation. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 11/16 2010.02 - Rev.A BD9018KV Technical Note Input & output equivalent circuits VCCCL BOOT VREG5 (VREG5A) OUTL 5k SYNC OUTH DGND SW 205k 1pF RT 150 EXTVCC EN 172.2k 135.8k 10k 10k Fig. 33 www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 12/16 2010.02 - Rev.A BD9018KV Operation notes Technical Note 1Absolute maximum ratings Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc. Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider taking physical safety measures to protect the circuits, such as adding fuses. 2GND electric potential Keep the GND terminal potential at the lowest (minimum) potential under any operating condition. Moreover, all terminal voltages except SW must not become less than GND. In any case where any terminal voltages become less than GND, apply measures such as adding by-pass route. 3Power Dissipation Pd The power dissipation exceeding its rating would deteriorate the IC characteristics, such as the decrease in the current capability due to the temperature rise of the chip, and hence lead to less reliable. Thus please allow enough margins from the power dissipation rating. 4Input supply voltage Input supply pattern layout should be as short as possible and free from electrical interferences. 5Electrical characteristics The electrical characteristics of the specifications may vary with the temperature, supply voltage and external circuit, etc. It is recommend to thoroughly verify including transient characteristics. 6Thermal shutdown (TSD) This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run beyond allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and turning all output pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal operation. Note that the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no circumstances should the TSD be used in set design or for any purpose other than protecting the IC against overheating 7Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts between the power supply and GND. 8 some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element In damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the GND. In order to avoid these problems, limiting VREG5 pin capacitance to 12F or less and inserting a Vcc series countercurrent prevention diode or bypass diode between the various pins and the Vcc is recommended. Bypass diode urr evention diode Vcc Pin Fig. 34 9Operation in strong electromagnetic fields Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction. 10For applications where the output-pin is connected with large inductive load, which counter-EMF (electromotive force) might possibly occur at the start up or shut down, add a diode for protection. 11Testing on application boards Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure to discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to or removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in the assembly process, and take similar antistatic precautions when transporting or storing the IC. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 13/16 2010.02 - Rev.A BD9018KV Technical Note 12GND wiring pattern When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND. 13The SW pin When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value. Connecting a resistor of several will reduce the electric potential. (See Fig. 35) Vcc BOOT OUTH SW R Vo OUTL DGND Fig. 35 14) The output FET The shoot-through may happen when the input parasitic capacitance of FET is extremely big. Less than or equal to 1200pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this character is affected by PCB layout and components. 15This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these Players with the N layers of other elements, creating a parasitic diode or transistor. Relations between each potential may form as shown in the example below, where a resistor and transistor are connected to a pin: With the resistor, when GND Pin A, and with the transistor (NPN), when GNDPin B: The P-N junction operates as a parasitic diode With the transistor (NPN), when GND Pin B: The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the parasitic diode described above. Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between circuits, and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P substrate) GND. Resistor TransistorNPN (PINA) (PINB) C B E (PINB) (PINA) B N C E GND P N P + P N P + P N + P N P substrate GND P + Parasitic element GND Parasitic element Parasitic element or transistor Fig. 38 Fig. 39 Parasitic element or transistor Fig. 36 16) Fig. 37 For applications where Vin and EN are directly connected, the output may overshoot. To avoid this issue it is recommended to select the lower side of the feedback resistor to more than 47k. This restriction does not apply if the EN is individually turned on when the VCC is greater than 4.5V. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 14/16 2010.02 - Rev.A BD9018KV Technical Note 17) Changing the switching frequency between the internal oscillator and external synchronization (SYNC) When the switching frequency changes from the internal oscillator to SYNC, one switching pulse might be skipped. In contrast, when the switching frequency changes from SYNC to the internal oscillator, one extra switching pulse might be added. This would cause the output voltage to be dropped or raised when the switching pulse is skipped or added extra, as shown in Fig. 40. The magnitude of the output voltage drop or rise depends on phase compensation design. Synchronous SW Output voltage Fig. 40 Output voltage fluctuation when the frequency switch Internal oscillator300kHzSYNC450kHz Start supplying pluses to SYNC terminal before EN is turned on, or after EN is turned on and Soft start time is passed, as shown in Fig. 41. SYNC EN Supply to SYNC before EN is turned on Vo Soft start time Supply to SYNC after Soft start time passes Fig. 41 Timing chart for changing from internal oscillator to SYNC 18) EN terminal There is a possibility that the output doesn't stand up when the charge remains in the output when EN is ONOFF, and OFFON again. Therefore, please turn on EN after Dischargeing it up to 1V the voltage of the output when you turn on EN again. Necessary time for Discharge: t calculates in the type in the under. 1 t = Co x Ro x ln [sec] Vo Vo: Output voltage, Co: Output capacitor, Ro: Output load www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 15/16 2010.02 - Rev.A BD9018KV Power dissipation vs. Temperature characteristics PD(W) 1.2 POWER DISSIPATIONPd [W] Technical Note VQFP48C 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150 AMBIENT TEMPERATORETa [] 1.1W 0.75W Stand-alone IC Mounted on Rohm standard board 70mmx70mmx1.6mm glass-epoxy board Fig. 42 Part order number B D 9 0 1 8 K V - E 2 Part No. Type/No. Package KV:VQFP48C Packaging and forming specification E2: Embossed tape and reel VQFP48C 9.00.2 7.00.1 36 37 25 24 Tape Quantity Embossed carrier tape 1500pcs E2 direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on 9.0 0.2 7.0 0.1 48 1 12 13 0.75 1.6MAX 1PIN MARK +0.05 0.145 -0.03 4 +6 -4 1.4 0.05 0.1 0.05 0.50.1 0.08 S +0.05 0.22 -0.04 0.08 0.50.15 1.00.2 0.75 Direction of feed M 1pin Direction of feed (Unit : mm) Reel Order quantity needs to be multiple of the minimum quantity. www.rohm.com c 2010 ROHM Co., Ltd. All rights reserved. 16/16 2010.02 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved. R1010A |
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